TimeWeaver for AURIX is a hybrid WCET analyzer that combines sophisticated static program analysis techniques (value + path analysis) with non-intrusive live tracing. Real-Time instruction level timings are extracted on-demand and extrapolated to identify the worst-case execution scenario.
The user simply provides the application ELF binary, specifies a function/task entry, and connects via network to the Infineon DAS Trace Server, communicating directly to the Infineon ED hardware. The hardware sends the MCDS trace data back to TimeWeaver which computes a worst-case execution path and time, visualizes the path and provides detailed reporting about timing contributions and trace coverage back to the user.
The WCET result can be used for timing verification or optimization (i.e. identify timing bottlenecks) in the considered code. An automatic tool qualification according to ISO 26262, DO-178B/C, IEC-61508 is possible.
TimeWeaver offers a powerful user-interface, with fully integrated graphical and textual views for control flow, analysis results, source code, assembly code, and configuration files. You can:
- Interactively explore analysis results
- Save and restore analysis scenarios
- Export customizable reports for documentation and certification purposes
- Start all analyses from the same GUI and handle all the tools with the same look and feel
The Business Case is Clear
Violating timing constraints on embedded applications can have severe consequences for the functional behavior of the application. A malfunctioning system can cause unreasonable risk to life and property and must be avoided. Traditional approaches like dynamic end-to-end measurements are expensive, the test-end criterion is not clear and cannot provide worst-case guarantees.
TimeWeaver for AURIX works without the need for an expensive debugger solution. It connects directly to the Infineon DAS Trace Server, controls the ED hardware and receives back the required tracing information which is automatically processed in TimeWeaver’s trace and WCET analyzer. This approach predicts a worst-case execution scenario statically using the dynamically observed instruction level timings. This will help the software and verification/test engineer to increase the code quality, as well as fulfill the highest timing related safety requirements.