ARM – Neoverse N12019-08-09T15:16:07+00:00

Project Description

ARM – Neoverse N1 System Development Platform

What the Neoverse N1 SDP Does

The Neoverse N1 System Development Platform (SDP) is an N1 CPU-based development platform for hardware prototyping, software development, system  alidation and performance profiling/tuning.

N1 SDP platform consists of a hardware board with Neoverse N1 SoC running a complete Armv8.2-A open-source software stack that’s available through GitHub and other hosting sites such as Linaro. N1 SoC has been developed using state-of-the-art 7nm manufacturing process targeting CPU frequencies from 2.6GHz (nominal) to 3GHz (overdrive).

N1 SDP delivers to developers an Armv8.2-A development
platform with:

  • Two dual-core Neoverse N1 CPU clusters
  • N1 backplane fabric comprising coherent mesh interconnect
    (CMN-600), IO memory management unit (MMU-600) and generic
    interrupt controller (GIC-600)
  • Real-time debug and trace capability using CoreSight SoC-400
  • Support for dual-channel DDR4-3200 memory
  • Support for X16 PCIe/CCIX Gen4 links for coherent chip-to-chip
    attach via CCIX
  • An SoC architecture compliant with Server Based System Architecture (SBSA) v3 and Server Based Boot Requirements

The N1 SDP software stack available through open-source
repositories, delivers to developers an out-of-the box Linux
software package running:

  • Trusted Firmware-A (TF-A)
  • AArch64 Linux kernel with supporting file systems and
    drivers including those for PCIe/CCIX, chip-to-chip boot and
    symmetric multi-processing (SMP)
  • Universal Extensible Firmware Interface (UEFI) and Advanced Configuration and Power Interface (ACPI) support

It enables:

  • AArch64 kernel and tools development for Neoverse N1 platform
  • PCIe Gen4 and CCIX ecosystem development
  • Secure boot, OS and hypervisor development through Trusted Firmware-A
  • Development of coherent acceleration use cases using a CCIX compatible FPGA board that connects over CCIX link to the Neoverse N1 board
  • Real-time debug using P-JTAG and 32-bit trace debug

Develop Next-Gen System-on-Chip Design

Neoverse N1 SDP provides an excellent environment for developing the next generation of system-on-chip designs. Through a range of plug-in options, hardware and software applications can be developed and debugged. Moreover, with N1 SoC supporting full-speed operation for the N1 CPUs, fully-sized caches and generous amounts of memory bandwidth with the latest optimized system IP, realistic workload analyses can be performed to optimize software performance for production environments. N1 SDP is also one of the earliest available boards for connecting CCIX-enabled FPGAs or custom ASICs for developing new software models for coherent acceleration use cases.

Through the use of an appropriate PCIe riser card, two Neoverse N1 boards can be connected to each other using the CCIX link to emulate a dual-socket symmetric multi-processor (SMP) configuration.

A microcontroller-based configuration mechanism provides an easy, USB-based plug-and-play method for programming software, firmware and FPGA images into the system flash memory from an attached PC.

Neoverse N1 SDP is available in Q2 2019 as part number V2M-N1SDP-0342A.

Features of N1 SoC and Board

SoC Compute subsystem
• Dual-core, dual-cluster SMP configuration with a total of 4 N1 CPUs
• N1 CPU
◦◦ 2.6–3GHz maximum operating speed
◦◦ Caches (per core): L1 64kB Icache and Dcache, 1MB private L2 cache
◦◦ Caches (shared): shared 2MB L3 between all cores, 8MB shared system level cache (SLC), both can be configured down to size zero • Internal CMN-600 interconnect operating up to 2GHz
• GIC-600 and MMU-600 for interrupt management and IO virtualization support
• 2 x 72-bit DMC-620 memory controller for dual channel DDR4 3200MHz memory
• Two Cortex-M7 CPUs functioning as System Control Processor (SCP) and Management Control Processor (MCP) for supporting event logging, power and device management
• CoreSight SoC-400 functional debug and trace capability Board expansion support with corresponding external ports
• 1x CCIX Gen4 x16 port
◦◦ Support for one x16 CCIX capable adaptor card
• 1x PCIe x16 Gen3 link to 48-lane switch with downstream slots and peripherals
◦◦ x16 PCIe Gen3
◦◦ x8 PCIe Gen3
◦◦ x1 PCIe Gen3
◦◦ x1 Gigabit Ethernet
◦◦ x1 SATA III
◦◦ x1 USB 3.0
• Master-slave ThinLink interfaces to low speed peripheral in the IO FPGA
◦◦ UART/I2C interfaces routed to the Platform Controller Chip (PCC)
• 32-bit MIPI-60 Trace port, JTAG debug port plus Arm CoreSight 20 JTAG connector for debug only

Cortex-M4 Motherboard Configuration Controller (MCC) for board powerup, reset and configuration including IOFPGA configuration
• Simple drag and drop configuration via USB debug port
• Located in always-on power domain of the board
• Static memory bus connection to the IOFPGA
• Reads N1 SoC temperature and controls cooling fans

Cortex-M4 PCC for enterprise SoC/board management
• Located in the always-on power domain of the board
• Static memory bus connection to the IOFPGA
• Dual 7-segment LED display

• AXI Thin Links Master and Slave interface to the N1 SoC
• HDLCD for simple low-resolution output from the N1 cores or PCC (boot) + I2S audio
• HDMI connection driven by HDLCD controller
• APB energy meter registers, for processor voltage control and current monitoring
• UART ports, system registers, Watchdog and Real Time Clock
• 8 user DIP switches and 8 LEDs
Programmable oscillators and onboard power and reset push buttons

Software Overview for Neoverse N1 SDP

  • The following are the key software components available from Arm with the N1 SDP:
    SCP Firmware
    • System initialization, cold boot flow, control clocks and device management
  • Trusted Firmware-A
    • Provides a reference implementation of secure world software for Armv8-A including a Secure Monitor executing at Exception Level 3 (EL3)
  • 64-bit Linux drivers including those for PCIe/CCIX/ SMP, etc.
  • UEFI and ACPI support
  • Scripts for downloading various open-source components including Linux kernel